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Developer Divyansh Agrawal reports building Qwenputer, an experimental version of Qwen3.5 4B with a compiled RV32IM RISC-V CPU and addressable memory inside the model’s layers. The CPU reportedly passes official RISC-V tests and completed an 18-million-instruction free-running test without errors; those results come from the developer’s report, and independent verification is not described in the supplied material.
Developer Divyansh Agrawal says he has built Qwenputer, an experimental version of Qwen3.5 4B with a functioning 32-bit RISC-V CPU compiled into the model’s weights. The system uses the model’s Gated DeltaNet state as addressable memory, allowing it to run CPU instructions within model forward passes rather than calling an external computing tool or runtime.
Agrawal describes the CPU as an RV32IM core, with the Zba extension and a small unit for big-number arithmetic. It occupies 11 layers in front of Qwen3.5’s 32, according to the post. The report says the core passes official RISC-V tests, produces results matching the QEMU emulator, and ran 18 million instructions without an error in a free-running test, where it continued using its own outputs rather than being corrected by a reference machine.
The memory system is built from Gated DeltaNet (GDN) state, which Agrawal configures with a gate of 1, write strength beta of 1, and one-hot keys. In his account, those settings let the system preserve stored values and overwrite or retrieve specific rows. The model’s generated tokens form an execution trace: tokens identify a memory address and value, and a step token advances the CPU. Agrawal says the model can also run C and MicroPython code, though relatively slowly.
The CPU’s weights are set by a compiler that maps circuit operations into model components, rather than by training the model on CPU examples. Agrawal says the original Qwen weights remain unchanged, with the computer weights added separately. A small driver, RvChat, loads firmware into GDN state and keeps the CPU’s trace tokens out of Qwen’s layers. The project’s model, code and related materials are identified in the post as available through Hugging Face, ModelScope and GitHub.
A CPU Inside Model Layers
Qwenputer is a demonstration of a different way to combine language models and computation: instead of asking a model to call a calculator or a software tool, it places a CPU implementation inside the model’s own layers. If the reported behavior holds up under independent testing, the project suggests that recurrent state in a hybrid model can serve as fixed-size, addressable working memory for structured computation.
The result is experimental, not evidence that an ordinary Qwen3.5 model has become a general-purpose computer. The CPU is a purpose-built addition, and the report describes execution as slow for some programming tasks. Still, the approach could matter to researchers studying in-model computation, memory design and how reliably models can carry out long sequences of exact operations. It also raises evaluation questions: correctness over a test suite is useful, but broader evidence would be needed to establish performance across programs and operating conditions.
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How DeltaNet Became Memory
Qwen3.5 uses a hybrid architecture. Agrawal writes that three out of every four attention layers use Gated DeltaNet, a linear recurrent mechanism that updates a state matrix as tokens are processed. In the report’s description, that state normally acts as part of the model’s processing; Qwenputer configures it so selected rows can instead retain exact values and be read through one-hot queries.
The underlying idea of delta-rule memory predates this project. Agrawal cites a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber on linear transformers as fast-weight programmers. He presents Qwenputer’s contribution as making the memory exact and addressable enough to host a CPU in a production-model architecture. The supplied report does not provide a publication date, independent review or external replication of its performance claims.
“This ‘CPU’ runs completely within the forward passes of the model.”
— Divyansh Agrawal, Qwenputer developer
Independent Tests Remain Unreported
The performance figures and test results in the supplied material are claims by the project’s developer. It does not include independent test results, detailed benchmark methodology, hardware and runtime comparisons, or an external audit of the code. The report says programs match QEMU and that the CPU passed official tests, but does not identify the test versions or provide results in the excerpt.
It is also unclear how broadly the system handles programs beyond the examples and tests described, how its speed compares with conventional execution, and what practical limits apply to memory capacity or program length. The post notes that C and MicroPython run slowly and that the CPU is not a Linux-class system. Those qualifications mean the project should be understood as an experimental architecture demonstration, not a replacement for a conventional processor.
Replication Will Test the Claims
The immediate next step for readers and researchers is to inspect the model and code releases cited by Agrawal and attempt to reproduce the reported tests. Independent confirmation of instruction accuracy, long-run stability and performance would help establish how much computation the design can support beyond the developer’s stated results.
The supplied report does not announce a release schedule, external evaluation or follow-up milestone. Until more evidence is available, Qwenputer’s reported test results and programming capabilities remain attributable to its developer, while its broader usefulness and limitations remain open questions.
Key Questions
What is Qwenputer?
Qwenputer is an experimental version of Qwen3.5 4B that adds a compiled RISC-V CPU to the model’s weights, according to developer Divyansh Agrawal.
Does it use an external CPU or tool?
Agrawal says the CPU runs within the model’s forward passes and does not rely on an external tool call or runtime for its execution. The project does use the RvChat driver to load firmware and manage the execution trace.
How does the model store CPU data?
The system uses configured Gated DeltaNet state as memory. Agrawal says one-hot keys can address individual rows, while the CPU’s generated tokens carry addresses, values and step instructions.
How well has the CPU been tested?
The developer reports that it passes official RISC-V tests, matches QEMU on programs and completed an 18-million-instruction free-running test without errors. Independent verification is not provided in the supplied material.
Can Qwenputer replace a conventional computer?
The report does not establish that. Agrawal says the core is not a Linux-class chip and that C and MicroPython execution can be slow, describing an experiment rather than a general-purpose replacement.
Source: divagr.com
